This application relies for priority upon Korean Patent Application No. 2001-20768, filed on Apr. 18, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to a voltage level converting device, and more specifically to an on-chip system having a voltage level converting device serving to convert voltages between modules operating with different operating voltages.
In system design, realizing a system having multi-functions with low power consumption is an important concern with respect to mobility and multi-functions in system. Accordingly, it is important to lower the power supply voltage. Moreover, the power supply voltages have been separated such that they can be individually supplied, depending on various functions of internal blocks. For the purpose of achieving low power consumption in the system, it is desired that the constituent parts thereof be designed to reduce the power in accordance with an operating mode and be configurted in an architecture minimizing the power consumption. To reduce the power consumption according to the operating modes, a power-down mode and power-off mode are provided for the system having central processing unit (CPU), real time clock circuit, clock control circuit, memory control circuit, etc.
If the system enters the power-down mode, only the CPU in the system operates. At that time, the clock is not supplied for the rest of the functional blocks or modules, thereby reducing dynamic current due to the clock. Accordingly, the power consumed can be reduced. Further, if the system enters the power-off mode, the power supply voltage is interrupted in blocks or modules when the system is not in use, except in required blocks.
In case that the power supply voltage is separated between modules and is different for each module in the system, a leakage current can be generated due to differences in the power supply voltage level for a signal transferred between the modules. For instance, it is assumed that a signal is transferred from a first module operating in a voltage of 2.5V to a second module operating in a voltage of 3.0V, and a well-known complementary metal oxide semiconductor (CMOS) inverter is used as the input or reception circuit for the second module. If the transmission signal is at a high level, a N-channel MOS transistor can be completely turned on. However, the P-channel MOS transistor where gate voltage is 2.5V and source voltage is 3.0V is not completely turned off. Hence, a small amount of leakage current flows from the power supply voltage to ground voltage through the PMOS and NMOS transistors.
To prevent the leakage current caused by the voltage level difference, the system employs voltage level converting circuit generally referred to as a xe2x80x9clevel shifterxe2x80x9d. A well-known voltage level converting circuit in this field is shown in FIG. 1. Referring to FIG. 1, the voltage level converting circuit as an interface circuit between the modules converts a voltage level of an input signal IN transferred from a 2.5V module to a 3.0V module. Two inverters INV1 and INV2, two PMOS transistors MP1 and MP2, and two NMOS transistors MN1 and MN2 compose the circuit. As indicated in dashed line, the inverter INV1 operates in the operating voltage VDD1 of the 2.5V module, and the rest of the components operate in the 3.0V module.
It is assumed that the power supply voltage of the first module is interrupted in the power-off mode, while the power supply voltage of the second module continues to be supplied in the power-off mode. The voltage level converting circuit shown in FIG. 1 has a problem when the system enters the power-off mode. That is, the leakage current flows within the voltage level converting circuit in the power-off mode, which results in harm to the low power structure of the system.
Specifically, when the system enters the power-off mode, the power supply voltage of the module generating the input signal IN is interrupted. Thus, the input signal IN and a reversed input signal nIN are conducted to be floating status, so that the signals have unstable values. Because of the bistable characteristic of the voltage level converting circuit, nodes N1 and N2 try to retain current stable voltage level. However, a lot of leakage current can be generated at a critical point as the signals IN and nIN are changed to be unstable. For instance, in the case that the signals IN and nIN turn to voltage level of logic xe2x80x981xe2x80x99, the nodes N1 and N2 turn to logic xe2x80x980xe2x80x99, and the PMOS transistors MP1 and MP2 are turned on. Since the NMOS transistors MN1 and MN2 are turned on, a lot of leakage current flows from the power supply voltage VDD2 to the ground voltage.
It is, therefore, an object of the present invention to provide an improved voltage level converting circuit applicable to low power consumption.
It is another object of the present invention to provide a voltage level converting circuit for effectively preventing internal leakage current caused by an input signal in unstable status.
It is further another object of the present invention to provide an on-chip system employing a voltage level converting circuit capable of preventing leakage current generated when a power supply voltage of a transmitting module is interrupted.
In order to attain the above objects, according to an aspect of the present invention, there is provided an interface circuit which serves to convert voltage level between modules. The interface circuit includes a voltage level converting circuit referred to as a xe2x80x9clevel shifterxe2x80x9d. According to a preferred embodiment of the invention, the voltage level converting circuit includes an input control circuit allowing the voltage level converting circuit to operate a normal voltage converting operation in a normal operating mode while preventing a leakage current path of the voltage level converting circuit due to an unstable input signal in a power-off mode.
According to another embodiment of the invention, the voltage level converting circuit includes a current path cut-off circuit which allows the voltage level converting circuit to operate the normal voltage converting operation in the normal operating mode, like the input control circuit. Meanwhile, in the power-off mode, the current path cut-off circuit interrupts a ground path of the voltage level converting circuit in order to prevent a leakage current path of the voltage level converting circuit due to an unstable input signal.
In accordance with the present invention, there is provided an on-chip system. The system includes a first module operated at a first power supply voltage and blocked from the first power supply voltage in a power-off mode. A second module is operated at a second power supply voltage and is supplied with a second power supply voltage even in the power-off mode. An interface circuit is connected between the fist module and the second module. The interface circuit includes a level converting section having input transistors for converting a voltage level of the first power supply voltage provided from the first module to a voltage level of the second power supply voltage. The interface circuit also includes means for preventing the input transistors from being synchronously activated in response to a control signal when a signal provided from the first module is unstable in the power-off mode.
In one embodiment, the control signal is at a high level in a normal operating mode and at a low level in the power-off mode. The control signal can be created in a control signal generating circuit which includes an output terminal of the first module and a resistor connected between the output terminal and ground voltage. The control signal can be provided from a connecting node of the resistor and the output terminal. The output terminal of the first module can be at a high level in the normal operating mode and in a floating status in the power-off mode.
In one embodiment, the means for preventing the input transistors from being synchronously activated includes a first inverter for converting a signal provided from the first module and a second inverter for converting the control signal. An OR gate provides a gate signal provided from one of the input transistors in response to the output signals from the first and second inverters. An AND gate provides a gate signal provided from another of the input transistors in response to the control signal and the signal provided from the first module. The first inverter can operate at the first power supply voltage and the second inverter, the OR gate and the AND gate can operate at the second power supply voltage.
In another aspect, the invention is directed to a voltage level converting device which includes an input terminal for receiving an input signal of a first power supply voltage. A pair of cross-coupled transistors is connected to a second supply voltage, a first node, and a second node. A first input transistor is connected between the first node and ground voltage, and a second input transistor is connected between the second node and ground voltage. An input control circuit prevents the first and second input transistors from being synchronously activated by an input signal in an unstable status in response to a control signal applied from the outside, when the input signal is in an unstable status.
In another aspect, the invention is directed to an on-chip system which includes a first module operated at a power supply voltage and blocked from the first power supply voltage in a power-off mode and a second module operated at a second power supply voltage higher than the first power supply voltage and supplied with the second power supply voltage even in the power-off mode. An interface circuit is connected between the first and second modules. The interface circuit includes a pair of cross-coupled transistors connected to the second power supply voltage, a first node and a second node. The first and second input transistors are connected between the first node and ground voltage and between the second node and the ground voltage. An input control circuit exclusively activates the first and second input transistors in response to a control signal applied from the outside when an input signal from the first module is in an unstable status in the power-off mode.
In another aspect, the invention is directed to an on-chip system which includes a first module operated at a first power supply voltage and blocked from the first power supply voltage in a power-off mode and a second module operated at a second power supply voltage higher that the first power supply voltage and supplied with the second power supply voltage even in the power-off mode. A plurality of voltage level converting circuits are serially connected between the first and second modules. Each of the voltage level converting circuits includes a pair of cross-coupled transistors connected to the second power supply voltage, a first node and a second node. The converting circuits also include first and second input transistors connected between the first node and a third node and between the second node and the third node, wherein the first input transistor is controlled by an input signal provided from the first module and the second input transistor is controlled by an inverted signal of the input signal. An inverter is connected to the first node for providing an output signal corresponding to the input signal. A current path cut-off circuit is connected between the third node and ground voltage to interrupt a current path between the third node and the ground voltage when an input signal of the respective level converting circuits is in an unstable status and the power-off mode.
In accordance with another aspect, the invention is directed to an on-chip system which includes a first module operated at a first power supply voltage and blocked from the first power supply voltage in a power-off mode and a second module operated at a second power supply voltage higher than the first power supply voltage and supplied with the second power supply voltage even in the power-off mode. A voltage level converting circuit is connected between the first and second modules. The voltage level converting circuit comprises a pair of cross-coupled transistors connected to the second power supply voltage, a first node and a second node. The converting circuit also includes first and second input transistors connected between the first node and the third node and between the second node and the third node, wherein the first input transistor is controlled by an input signal provided from the first module and the second input transistor is controlled by an inverted signal of the input signal. An AND gate receives a signal from the first node and control signal from the outside and provides an output signal corresponding to the input signal. A current path cut-off circuit is connected between the third node and ground voltage to interrupt a current path between the third node and the ground voltage when an input signal of the respective level converting circuits is in an unstable status and the power-off mode.
As is apparent from the foregoing, according to the circuit of the invention, it is possible to prevent the leakage current path of the voltage level converting circuit converting the voltage between modules being operated at different operating voltages.